In the field of the manufacturing of integrated circuits, processing of batches of semiconductor wafers are conventionally carried out, each integrated circuit constituting a small area, generally rectangular, of each wafer. A plurality of identical patterns are repeated on the same wafer. However, in order to be able to check that there was no drift during the manufacturing process with respect to predetermined parameters, one generally provides for some free rectangles formed in the wafer for inserting test patterns designed for quickly checking the features typical to the wafer and to the specific manufacturing batch. Those test patterns may serve for the checking of the processing parameters when the wafer is completed, before being put into a casing, or for carrying out tests during intermediary steps of the manufacturing process, either for correcting the defects already existing in the previous steps, or for deciding whether the wafer is to be discarded before carrying out further manufacturing steps. In any case, the results of this test are used for determining the specific setting of the parameters of the following batch which must theoritically be processed with the same method.
Among the major parameters that one wishes to determine, are the parameters relative to the conduction per surface unit. Indeed, as it is often the case for an integrated circuit, the various layer portions intervene with respect to their surface features.
The physical effects taking part in the current flowing in the semiconductive layers are all the more complex as the designed sizes of those layers are smaller. While the surface of the elementary components (diodes, transistors, resistors) is reduced because of the advancement of the manufacturing technologies, particularly the photolithography, the physical surface effects (current, capacitors) further present the following effects:
periphery effects for elongated and narrow patterns, PA1 wedge effects for square patterns. PA1 connecting together to a first terminal the first contacts of the components associated with a first face of the test patterns; PA1 connecting the other contacts of the components associated with a second face of the patterns to a second terminal through measurement means of an electrical parameter; PA1 applying a current supply between the first and second terminals; PA1 measuring the current flowing through each test pattern; PA1 calculating therefrom the surface effects relative to the X and Y periphery, as well as the wedge effects.
On the other hand, an unavoidable drift occurs while manufacturing of those layers, between the design of the patterns and their implantation into silicon.
This drift directly depends upon the manufacturing process. It may be positive or negative. It is also scattered because of the variations of the manufacturing parameters.
This drift includes the inaccuracies in the implementation of all the steps of a given process: the implementation of the masks (positioning margin), the selection levels (over-etching of the resins in case of a resin mask, lateral extensions of oxide in the LOCOS technologies), and the steps of diffusion or implantation/annealing (lateral diffusions).
It is essential in any manufacturing process to be able to identify and distinguish those various effects (surface, perimeter, wedge) both in nominal value and in scattering, and to be able to study their evolution as a function of time. For this purpose, physical measurements carried out by means of microscopy or spreading resistance analysis permit occasional determination of those effects, but they are too complex for a statistical follow-up.
The use of an electrical test process carried out on suitable patterns permits a faster and more utilizable approach of those effects, since it provides for results that are of great interest for the circuit designers.
Those results are shown in the form of particular electrical parameters associated with geometrical parameters. The following units and notations are usual:
______________________________________ Electric variable Surface Periphery Wedges ______________________________________ Current densities A/.mu.m.sup.2 A/.mu.m A/wedge Junction capacitors or oxide capacitors f/.mu.m.sup.2 f/.mu.m f/wedge Diffusion charges C/.mu.m.sup.2 C/.mu.m C/wedge ______________________________________ (the abbreviation .mu.m stands for micrometer).
Those information are compulsory for the design since they permit the optimization of the elementary component design (transistors, diodes, etc.) within a given technology, resulting in a considerable gain in time and costs because of the substantial decrease in the number of tests carried out before reaching the desired optimum.
On the other hand, they are a complementary analysis tool for the teams in charge of optimizing the manufacturing processes.
Test patterns such as illustrated in FIGS. 1A and 1B, are currently used.
FIG. 1A shows a first test pattern. In this figure, the frame 1 drawn in solid lines represents the drawing of a mask used for forming or delimiting a layer and the frame 2 drawn in dotted lines represents the pattern resulting from this operation.
FIG. 1B shows a second test pattern associated with the first one. Similarly, the frame 3 shows a layer delimitation mask and the frame 4 drawn in dotted lines shows the obtained structure.
The structures of FIGS. 1A and 1B are specific in that they have periphery/surface ratios of unlike values. For using those structures, one introduces them into an elementary electrical component of an integrated circuit (resistor, transistor, etc.), so that a current is forced to flow perpendicularly to said layers. Under the same voltage conditions, one measures the currents I1 and I2 appearing at the terminals of said layers, in direct current or alternating current according to the type of structure. Once those currents I1 and I2 have been measured, and the designed surfaces SD1 and SD2 of the two patterns as well as peripheries PD1 and PD2 of those patterns being known, one determines the current densities JS and JP respectively associated with the surface and periphery effects of both structures with the following equations: EQU JS.times.SD1+JP.times.PD1=I1 EQU JS.times.SD2+JP.times.PD2=I2
It will be noted that for the writing of both equations, the wedge effects have been neglected.
This method presents some drawbacks. As a matter of fact, one can notice in the obtained results an important inaccuracy which is due to the fact that the wedge effects have not been taken into account. This inaccuracy does not permit the application of results to the design optimization of small-size components, wherein the wedge effects are preponderant. Furthermore, it involves a systematic and an a priori non-appraisable error in the design of components having large sizes. This method does not permit either to distinguish the effects in X and in Y of a periphery.
One object of the instant invention is to provide for a new test pattern structure permitting to supply, by means of simple and fast calculations, the voltage densities associated with the surface effects, X periphery, Y periphery and wedge effects for layer portions of an integrated circuit.